The present inventive concepts relate to cell designs in circuits, and more particularly, cell swapping techniques, devices, and systems based on a ceiling determination, a floor determination, and cell attribute weighting criteria.
Conventional integer division hardware must make a tradeoff between less area and better latency. It is difficult or impossible to achieve both low die area usage and low latency using convention techniques. Floating point capability and related hardware are conventionally separate from the integer division hardware, which has the effect of increasing the die area. Embodiments of the present inventive concept address these and other limitations in the prior art.